Signal processing method and apparatus and disk device using the method and apparatus

ABSTRACT

A signal processing circuit having a data sync signal detector and a disk device. Input data read from a magnetic disk is input to a data discriminator. A data discrimination output constituting a code bit output discriminated by the data discriminator is input to a post-coder the output of which is input to a decoder and a (1+D) processing unit. The processed output of the processing unit is input to an error detection/correction unit and separated into bit strings of odd numbered bits and even numbered bits, divided into groups. An error detection/correction output is input to a data sync signal detector, and matched against a sync pattern. When the number of coincident groups is greater than a threshold value, a sync signal is output and upon detection causes the decoder to demodulate the data.

The present application is a continuation of application Ser. No.09/400,856, filed Sep. 21, 1999; which is a continuation-in-part ofapplication Ser. No. 08/948,942, filed Oct. 10, 1997, now U.S. Pat. No.6,125,156, the contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

The present invention relates to a signal processing technique, and adisk device such as a magnetic disk drive or a magneto-optic diskdevice, or more in particular to a data sync signal detection techniqueand a disk device using a data sync signal detection and a disk deviceusing a data sync signal detection technique with an improved data syncsignal detection rate in which the data sync signal can be detected evenin the presence of a data discrimination error in the data sync signalfield of the data read from the disk device and discriminated.

FIG. 20 shows an example of the recording format for a magnetic diskdrive. The data includes an ID field and a DATA field for each sectorproviding a unit storage area. The ID field and the DATA field eachinclude a PLO (Phase Locked Oscillator) SYNC field 91 for pull-in of aPLL (phase locked loop), a data sync signal 92 for detecting thestarting position of an ID (address information) or data for producing ademodulation timing signal of a modulated code, an ID field forrecording/reproducing the ID information or a DATA field 93 forrecording/reproducing the data actually, and a CRC field or an ECC field94 for error detection and correction. Also, there is a GAP field 95providing a pattern for absorbing various delay time between the IDfield and the DATA field or between sectors.

It is well known that accurate detection of the data sync signal 92 isvery important for the subsequent code demodulation of the ID or DATAfield 93. In other words, even in the case where the decode data in theID or DATA field 93 has a very satisfactory error rate, a detectionerror of the data sync signal 92 which is normally about several bytescauses inaccurate code demodulation of the ID or DATA field 93 ofseveral tens to several hundred bytes.

A method using a pattern having no continuous data inversion as a datasync signal is disclosed in JP-A-8-096312.

In the method disclosed in U.S. Pat. No. 5,844,920, there are providedpatterns (marks) for data synchronization at two points, between which agap (no data) or data are filled. In the case where such a gap is filledwith data and the data sync detection is effected by the second datasync pattern, the data between the data sync patterns is restored bycorrecting an erasure pointer for the data error correction code. Theprovision of data sync patterns at two points makes possible data syncdetection even in the case a thermal asperity (TA) occurs in the datasync pattern field.

Further, in order to improve the reproduction performance, there hasbeen proposed a MTR (Maximum Transition Run) code in which the number ofcontinuous magnetization inversions is limited, according to thereference “Maximum Transition Run Codes for Data Storage Systems”, IEEE.Trans. Mag. Vol. 32, No. 5, September 1996, written by J. Moon and B.Brickner.

In a method of data sync detection for a signal processing apparatushaving a configuration as shown in FIG. 21 examined by the presentinventors, input data 511 are discriminated by a data discriminator 501,and a data discrimination output 512 is subjected to a predeterminedpost-code processing (bit operation) in a post-coder 502. In thepost-code processing, the processing corresponding to the pre-codeprocessing at the time of recording not shown is performed. This is inorder to assure correspondence between the data coding at the time ofrecording and the decoding at the time of reproduction. According to themethod disclosed in JP-A-9-223365, it is possible to perform theprocessing equivalent to the post-code processing at the time ofoutputting the result of the state transition in the data discriminator501. Therefore, the post coder 502 is not always necessary as anindependent component element. Nevertheless, the method of JP-A-9-223365is also considered to functionally include an independent post coder 502having the post-coding operation separated from the data discriminator,or a post-code processing means for simply passing through the code fromthe data discriminator. The post-code output 513 is applied to a decoder504. Also, the same post-code output 513 is applied to a data syncsignal detector 503 and compared with a predetermined sync pattern 514.When they coincide with each other, a data sync signal 92 is detected,and applied to the decoder 504 as a sync signal detection output 516.With this signal as a decode timing signal, the decoder 504 performs thedecode operation thereby to produce an output data 517.

The data sync signal detector 503 is so configured, as disclosed in U.S.patent application Ser. No. 08/948,942, that the data-discriminated codestring is divided into groups of a bit string of odd numbered bits and abit string of even numbered bits, and each group is compared with a syncpattern for coincidence. In the case where the number of coincidentgroups exceeds a predetermined threshold value 515, it is determinedthat a data sync signal has been detected. This data sync signaldetection processing can exhibit a high ability of data sync signaldetection.

On the other hand, the MTR code described above is the code in which therecording data is inverted by 1. When using such a code, the pre-codeprocessing is the (1/(1+D)) processing (an input value and an outputvalue delayed by a predetermined time are added in modulo 2 as an outputvalue). The corresponding post-coding process is the (1+D) processing(an input value and an input value delayed by a predetermined time areadded in modulo 2 as an output value). The use of the MTR code improvesthe data reproduction performance and shortens the error length. Even inthe case where the error in the data discriminator 501 is one bit,however, it presents itself as an error of two continuous bits after the(1+D) processing of the post-coder 502. The data sync signal cannot besuccessfully detected, therefore, even when a code string is dividedinto a bit string of odd numbered bits and a bit string of even numberedbits.

In the case where a one-bit data error of the data sync signal 92 occursin the configuration shown in FIG. 21, therefore, the data sync signalis detected erroneously, followed by the ID and DATA fields 93 allerroneous. (If a permanent bit drop-off in the data sync signal unitoccurs due to a defect of the medium, etc. data for one sector cannot becorrectly reproduced.)

As described above, an erroneous detection (detection not at rightposition or detection at an erroneous position) of the data sync signalat the head of data causes not merely the erroneous detection of thedata sync signal but also all the subsequent decode processing ofseveral hundred bytes become erroneous, resulting in the technicalproblem that the error rate of the whole apparatus is considerablydeteriorated.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a signal processingtechnique capable of reducing the error in the data sync signaldetection.

Another object of the invention is to provide a signal processingtechnique capable of improving the data sync signal detectionperformance of a data sync signal detector with the improvement in thereproduction performance of the data field.

Still another object of the invention is to provide a signal processingtechnique capable of reducing the circuit size with a simpleconfiguration of the data sync signal detector.

A further object of the invention is to provide a magnetic disk drivecapable of improving the recording density by employing a signalprocessing system including a Maximum-Likelihood or Viterbi decodingmeans and reducing the error rate by the improved detection performanceof the data sync signal at the same time.

A yet further object of the invention is to provide a magnetic diskdrive capable of reducing the production cost by reducing the circuitsize of the signal processing system for detecting the data sync signaland reducing the error rate by the improved detection performance of thedata sync signal at the same time.

According to one aspect of the invention, there is provided a data syncsignal detection system for a signal processing apparatus including adata discriminator for outputting a bit string of data, a post-coder forperforming a predetermined post-code processing (bit operationprocessing) on the bit string, a decoder for decoding the post-coded bitstring thereby to reproduce the data, the system comprising: a (1+D)processing unit for performing the processing of adding, in modulo-2, aninput value of the bit string of the code input to the decoder to avalue delayed a predetermined time from the input value ((1+D)processing) and producing an output value, a separator for dividing thebit string of the code containing data sync signals after the (1+D)processing into a bit string of odd numbered bits and a bit string ofeven numbered bits, each bit string being subdivided into one group ortwo or more groups separated with or without a bit string containing oneor more bits of an arbitrary pattern interposed there between, at lastone matching unit for comparing or matching the output of each groupwith or against a corresponding predetermined sync pattern anddetermining a coincidence or non-coincidence, and a decision unitsupplied with the output from each matching unit for outputting a datasync signal detection signal to the decoder in the case where the numberof coincident groups is equal to or more than a predetermined thresholdvalue.

Also, an error detection/correction unit is interposed between theseparator and each pattern matching unit for detecting and correcting anerror of the output code separated into a bit string of odd numberedbits and a bit string of even numbered bits and matching the pattern ofthe code bit string thus corrected against a predetermined sync pattern.

As a result, a sync pattern capable of error detection and correctionwith the data inversion not continuous is selectively used as apredetermined sync pattern.

According to another aspect of the invention, there is provided a datasync signal detection apparatus comprising a data discriminator forproducing a data bit string, a detector for detecting a data sync signalfrom the data bit string output from the data discriminator, a separatorfor dividing the raw data sync pattern into predetermined bit groups, amatching unit for matching each pattern with a predetermined syncpattern, and an error detection and correction unit associated with eachgroup for detecting and correcting an error of the output from eachgroup, wherein a code string for which the discrimination error has beencorrected is matched against the data sync pattern thereby to detect adata sync signal. This detection apparatus is not provided with the(1+D) processor described above. Instead, the code bit string containingthe data sync signals after post-processing is divided into groups, foreach of which the discrimination error is detected and corrected, andthen each group is matched against a predetermined data sync pattern.

Other objects, features and advantages of the present invention willbecome apparent from reading the description of the followingembodiments of the invention taken in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a signal processing apparatusaccording to an embodiment of the invention.

FIG. 2 is a block diagram showing a signal processing apparatusaccording to another embodiment of the invention.

FIG. 3 is a block diagram showing a signal processing apparatusaccording to still another embodiment of the invention related to theembodiment shown in FIG. 1.

FIG. 4 is a diagram useful for explaining an error pattern in the outputof a data discriminator according to a third embodiment.

FIG. 5 is a diagram showing a polynomial of degree 5 used with asyndrome calculator according to the embodiment of FIG. 9.

FIG. 6 is a diagram for explaining a configuration of a 9-bit syncpattern used with the embodiment of FIG. 9.

FIG. 7 is a diagram for explaining the relation between an errorposition and a syndrome value for each error pattern according to theembodiment of FIG. 9.

FIG. 8 is a diagram for explaining the relation between an errorposition and a syndrome value for each error pattern according to theembodiment of FIG. 10.

FIG. 9 is a block diagram showing a signal processing apparatusaccording to a further embodiment of the invention related to theembodiment shown in FIG. 2.

FIG. 10 is a block diagram showing a signal processing apparatusaccording to a still further embodiment of the invention related to theembodiment shown in FIG. 2.

FIG. 11 is a block diagram showing a signal processing apparatusaccording to a yet further embodiment of the invention related to theembodiment shown in FIG. 2.

FIG. 12 is a diagram showing an example configuration of a syndromecalculator according to the embodiment shown in FIG. 9.

FIG. 13 is a diagram showing an example configuration of an errorcorrection circuit according to the embodiment of FIG. 9.

FIG. 14 is a diagram showing an example configuration of an errorcorrection circuit according to the embodiment of FIG. 10.

FIG. 15 is a block diagram showing an internal configuration of amagnetic disk drive according to a further embodiment of the invention.

FIG. 16 shows an example of a sync pattern used with a signal processingapparatus according to the invention.

FIGS. 17A and 17B are graphs showing an example characteristic of a datasync signal detector according to the embodiment of FIGS. 3 and 9.

FIGS. 18A and 18B are graphs showing an example characteristic of a datasync signal detector according to the embodiment of FIG. 10.

FIGS. 19A and 19B are graphs showing an example characteristic of a datasync signal detector according to the embodiment of FIG. 11.

FIG. 20 is a diagram for explaining an example format of the recordingdata in a magnetic disk device.

FIG. 21 is a block diagram showing a configuration of a signalprocessing apparatus useful for explaining the present invention.

FIG. 22 is a block diagram showing a signal processing apparatusaccording to still another embodiment of the invention.

FIG. 23 is a block diagram showing a signal processing apparatusaccording to yet another embodiment of the invention related to theembodiment of FIG. 22.

FIG. 24 is a block diagram showing a signal processing apparatusaccording to still another embodiment of the invention.

FIG. 25 is a flowchart showing a method of detecting the data syncsignal according to a yet further embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

Embodiments of the present invention will be described in detail belowwith reference to the accompanying drawings.

FIG. 1 is a block diagram showing a signal processing apparatusaccording to an embodiment of the invention.

In FIG. 1, input data 11 are input to a data discriminator 1, and a datadiscrimination output 12 providing a code bit output discriminated bythe data discriminator 1 is input to a post-coder 2 for performing apredetermined post-code processing. Further, a post-coder output 13 isinput to a decoder 4 and a (1+D) processing unit 5. A (1+D) processingoutput 18 is input to a data sync signal detector 3, and is comparedwith or matched against a sync pattern 14 by a predetermined method. Inthe case where the number of pattern coincidences is not less than athreshold value 15, a sync signal detection output 16 is output. Thesync signal detection output 16 is applied to the decoder 4 and gives adecode timing of the code string of the post-code output 13. As aresult, a decoded output data 17 is output from the decoder 4.

Alternatively, independently of the data reproduction system includingthe post-coder 2 and the decoder 4, it is also possible to configuresuch that the data sync signal is detected from the code string obtainedby subjecting the data discrimination output 12 to the post-codeprocessing and the (1+D) processing. In other words, the code stringconstituting the input to the decoder 4 is not used. However, this isnothing but a parallel arrangement of post-code processing andapparently equivalent to the configuration of FIG. 1.

A signal processing apparatus according to another embodiment of theinvention will be explained with reference to FIG. 2.

In FIG. 2, input data 11 are input to a data discriminator 1, and a datadiscrimination output 12 providing a code bit output discriminated bythe data discriminator 1 is input to a post-coder 2 for performing apredetermined post-code processing. Further, a post-code output 13 ofthe post-coder 2 is input to a decoder 4 and a (1+D) processing unit 5.A (1+D) processing output 18 of the (1+D) processing unit 5 is input toan error detection/correction unit 6. The error detection/correctionunit 6 separates the (1+D) processing output 18 into a bit string of oddnumbered bits and a bit string of even numbered bits, so that an erroris detected and corrected of the bit strings thus grouped. The errordetection and correction output 19 after error correction is input to adata sync signal detector 3, and compared with or matched against apredetermined sync pattern. In the case where the number of patterncoincidences is not less than a predetermined threshold value 15, a syncsignal detection output 16 is output. The sync signal detection output16 is input to the decoder 4 and gives a decode timing of the codestring of the post code output 13, whereupon a decoded output data 17 isoutput from the decoder 4.

As described above, the (1+D) processing is executed and the bit stringis separated into a bit string of odd numbered bits and a bit string ofeven numbered bits before detection of the data sync signal. In thisway, the number of the types of the error pattern can be reduced whileat the same time shortening the error pattern length. As a result, theerror detection and correction is easily realized, and the data syncsignal can be detected with a higher accuracy.

FIG. 3 is a block diagram showing a configuration of a signal processingapparatus according to the embodiment of FIG. 1 used for decoding MTRcodes.

This embodiment will be explained specifically with reference to FIG. 3.An 18-bit sync pattern is used.

In FIG. 3, the decoder 4 is a MTR decoder with not more than 3continuous “1s”.

The data discriminator 1 is a Maximum-Likelihood decoder or Viterbidecoder of EEPRML (Extended Extended Partial Response with MaximumLikelihood detection) type. This channel response is (1−D)(1+D)³. Also,assume that the data discriminator is optimized for use with the MTRcode described above. Two sync patterns “001111111100011000” and“110000000011100111” are available for the data discrimination output12.

The post coder 2 has the characteristic of (1+D). One 18-bit syncpattern “001000000010010100”, is available for the post code output 13.Also, the operation of the post-coder 2 ((1+D) processing) may beincluded for outputting the state transition of the data discriminator1, and “001000000010010100” may be output as the data discriminationoutput 12 without providing the post-coder 2. In such a case, too, thefunction of the post coder 2 can be considered to be included.

The (1+D) processing unit 5 arranged before the data sync signaldetector 3 is configured with a unit time delay circuit or cell 31 andan exclusive OR circuit 32. The post-code output 13 is applied to theunit time delay cell 31 and the exclusive OR circuit 32. Also, theoutput of the unit time delay cell 31 is input to the remaining inputterminal of the exclusive OR circuit. The output of the exclusive ORcircuit 32 constitutes the (1+D) processing output 18. The sync patternin the (1+D) processing output 18 is given as a 18-bit pattern of“001100000011011110”.

The (1+D) processing output 18 is applied to a shift register 21 in thedata sync signal detector 3. The shift register 21 has a 17-bitconfiguration. This is in order to selectively use a 9-bit pattern as async pattern. Nine bits including every other bit of the shift register21 are output as a shift register output 22. By use of the values ofevery other bit of the shift register 21, the (1+D) processing output 18can be divided into two groups of a bit string of odd numbered bits anda bit string of even numbered bits for each operation clock not shown.The sync pattern in the shift register output 22 is one of the two 9-bitpatterns of “010001011” and “010001110”.

The shift register output 22 is input to a pattern matching unit 27 iand a pattern matching unit 27 j, and matched against the sync patternsof a sync pattern holder 26 i and a sync pattern holder 26 j,respectively. Each sync pattern is given as one of the sync patterns 14.The sync pattern holder 26 i holds the 9-bit pattern of “010001011”, andthe sync pattern holder 26 j holds the 9-bit pattern of “010001110”. Inorder to assure the same timing of the outputs of the pattern matchingunit 27 i and the pattern matching unit 27 j, the output of the patternmatching unit 27 i is delayed through a unit time delay circuit 28 b andinput to a majority decision logic circuit (decision circuit) 29.

The majority decision logic circuit 29 compares the number ofcoincidences between the two pattern matching results with the value ofthe threshold level 15, and in the case where the number of coincidencesof the pattern matching result is not less than the threshold value 15,the sync signal detection output 16 is output to the decoder 4. In thiscase, the threshold value 15 is given as 1, and therefore a two-input ORcircuit can be used.

The sync signal detection output 16 gives a decode timing to the MTRcode decoder 4. As a result, the correct decode operation is realizedthereby producing the output data 17.

Now, with reference to FIG. 4, the error patterns generated in theembodiment of FIG. 3 will be explained. In FIG. 4, the column to theextreme left lists error patterns of the data discrimination output 12in the data discriminator 1 (EEPRML), where x designates an error bit,and 0 a non-error bit. Six patterns x, xx, xxx, x0x, x00x and x000x areshown, of which five patterns other than xxx develop an error. Eacherror pattern (error event) is defined as an error pattern that canoccur between the time when the state transition path in the Viterbidecoder is displaced from the original path by error and the time whenit again comes to coincide with (returns to) the correct path.

The leftmost column but one represents the distance of each errorpattern code, which is an indication of the degree of likelihood oferror occurrence. The smaller the distance, the easier the error occurs.

The third column form the left represents the ratio of error occurrencein the sync pattern used in the embodiment of FIG. 11 described laterand the immediately preceding PLO SYNC pattern, or specifically, theratio of error occurrence in the 128-bit pattern of“10101010101010101010101010101010101010101000100100000101001010101010101010101010101010101000100000001001010010001 0101010101010”in the post-code output 13. The 18 bits (underlined portions) from eachof the 43rd bit and the 93rd bit of the pattern described above are thesync patterns. Originally, the pattern xxx is most likely to develop anerror. Since the selected patterns have no portion where the datainversion is continuous (i.e. the portion where 1 continues such as“11”), however, the EEPRML optimized to the MTR code with the datainversion limited to 3 bits or less prevents the occurrence of the errorpattern xxx. Thus, in this case, the occurrence of the error pattern xrepresents about 90% of all the error patterns. The bit error rateinvolved (the ratio of error event to the total number of bitsreproduced) is 0.0004. Thus, in the range of 10⁻⁶ to 10⁻⁸ where the biterror rate is lowest, for example, the ratio of occurrence of a longerror pattern such as x000x is still lowered to a degree negligible.About the same can be said of the sync patterns used in the embodimentsof FIGS. 3, 9, 10. Also for the embodiments of FIGS. 9, 10, 11 describedlater, refer to FIG. 4.

The fourth column from the left indicates each error pattern in thepost-code output 13.

The fifth column from the left indicates each error pattern in the (1+D)processing output 18 for data sync signal detection.

The sixth column from the left indicates each error pattern in the (1+D)processing output 18 after being divided into a bit string of oddnumbered bits and a bit string of even numbered bits for detecting thedata sync signal, i.e. each error pattern in the shift register output22. The error pattern of x in the data discrimination output 12indicates that an error (xx) of two continuous bits appears either inthe bit string of odd numbered bits or the bit string of even numberedbits in the shift register output 22.

From these facts, it can be understood that the provision of the (1+D)processing unit 5 anew for detecting the data sync signal can remarkablyimprove the detection rate of the data sync signal 92, because afterdivision into a bit string of odd numbered bits and a bit string of evennumbered bits, one of them contains no error even when a 1-bit error (x)representing about 90% of the error patterns occurs.

A specific performance will be explained with reference to FIGS. 17A,17B. FIGS. 17A, 17B are graphs showing the performance of the embodimentof FIG. 3 in computer simulation.

In FIG. 17A, the abscissa represents the signal-to-noise ratio of theinput to the Maximum-Likelihood or Viterbi decoder, and the ordinate thebit error rate and the detection error rate of the data sync signal. Acharacteristic curve 175 represents the bit error rate of the data inthe data discrimination output 12. This is the characteristic obtainedwhen the data is regarded as random one. A characteristic curve 171, onthe other hand, represents the characteristic of the detection errorrate of the data sync signal in the case where the process of detectingthe data sync signal is executed under the condition that all the 18bits of the sync pattern are coincident. A characteristic curve 172represents a method of a reference technique not including the (1+D)processing unit 5 for detection of the data sync signal, which is thecharacteristic of the detection error rate of the data sync signal inthe case where the process of detecting the data sync signal is carriedout under the condition that one of the 9-bit patterns divided into abit string of odd numbered bits and a bit string of even numbered bitsis coincident. A characteristic curve 173 represents a characteristic ofthe detection error rate of the data sync signal in the case where theprocess for detecting the data sync signal is carried out under theconditions of the embodiment of the invention shown in FIG. 3. It isseen that an improvement of about 2 dB is attained in terms ofsignal-to-noise ratio as compared with the method of the referencetechniques.

In FIG. 17B, the abscissa represents a bit error rate in the datadiscrimination output 12, and the ordinate the detection error rate ofthe data sync signal. This graph is the result of replotting the graphof FIG. 17A with the characteristic curve 175 as the abscissa. Thecharacteristic curve 176 corresponds to the characteristic curve 171,the characteristic curve 177 corresponds to the characteristic curve172, and the characteristic curve 178 corresponds to the characteristiccurve 173. Let Be (abscissa) be the rate of occurrence of the errorevent to the total number of output bits in the output of the datadiscriminator 1, and Se (ordinate) be the rate of occurrence of the datasync signal detection error to the number of data sync signal detectionrequests. Then, for the range of Be not more than 0.1, thecharacteristic curve 178 is approximated by equation (1) below.S _(e)=7B _(e) ^(1.20)  (1)

FIG. 9 is a block diagram showing a signal processing apparatusaccording to another embodiment to which the embodiment of FIG. 2 isapplied for decoding of the MTR code.

This embodiment will be explained with reference to FIG. 9.

The configuration of the data discriminator 1, the post-coder 2, thedecoder 4 and the (1+D) processing unit 5 in FIG. 9 is similar to thatof the embodiment shown in FIG. 3. Also, the same 18-bit pattern is usedas in the embodiment of FIG. 3. Thus, the sync pattern of each part upto the (1+D) processing output 18 is also the same.

The (1+D) processing output 18 is input to a shift register 21 in theerror detection/correction unit 6. The configuration of the shiftregister 21 is the same as that of the embodiment shown in FIG. 3. Thus,the sync pattern in the shift register output 22 is given as either ofthe two 9-bit patterns of “010001011” and “010001110”. The shiftregister output 22 is input to a syndrome calculator 23 a, a syndromecalculator 23 b, an error corrector 24 a and an error corrector 24 b.

The 9-bit sync pattern is configured with a 4-bit code and acorresponding 5-bit CRCC (Cyclic Redundancy Check Code) as shown in FIG.6. The CRCC is the 5-bit remainder after dividing the 4-bit code by agenerator polynomial. Thus, in the absence of an error, the remainder ofthe 9-bit sync pattern divided by the generator polynomial is alwayszero, while in the presence of an error, the remainder of the 9-bit syncpattern divided by the generator polynomial indicates a correspondingvalue. The value of this remainder is called the syndrome value. Unlessthe syndrome value is zero, it indicates an error and the error can bedetected. According to this syndrome value, the error position can bedetected and the error corrected (1 to 0, or 0 to 1).

Now, consider the sync pattern “010001011” as used herein. The leadingfour bits “0100” is the original code. The bit string “010000000”obtained by shifting the leading four bits is divided by the polynomialof degree 5 (X⁵+X⁴+X²+1) and the remainder constitutes the 5 bits“01011” of the CRCC. The remainder after dividing the sync pattern“010001011” by the polynomial of degree 5 (X⁵+X⁴+X²+1) is zero. Thisgenerator polynomial corresponds to e in FIG. 5.

The syndrome calculator 23 a uses the polynomial of degree 5(X⁵+X⁴+X²+1) expressed in e of FIG. 5 as a generator polynomial. In thesyndrome calculator 23 a, the dividing operation is performed using thegenerator polynomial (X⁵+X⁴+X²+1), and the remainder thereof is outputin five bits as a syndrome value 20 a.

A detailed example configuration of the syndrome calculator 23 a isshown in FIG. 12. In this case, the 9-bit input of the shift registeroutput 22 is divided at a time by the generator polynomial using 11exclusive OR circuits 301 to 311, and the 5-bit syndrome value 20 a isoutput. This calculation can be made by calculation-by-writing using amathematic operation. As a result, the syndrome value 20 a can be outputfor each shift register output 22 grouped and output as a bit string ofodd numbered bits and a bit string of even numbered bits according toeach operation clock not shown.

This is also the case with the syndrome calculator 23 b, which can beconfigured with h(X⁵+X⁴+X³+X²+1) of FIG. 5 corresponding to the syncpattern “010001110” as a generator polynomial.

Now, the syndrome value 20 a for error patterns will be explained withreference to FIG. 7. FIG. 7 shows ten error patterns of one bit or two.These are error patterns of two continuous bits often appearing in theshift register output 22, and at the end of the 9-bit group, constitutesa one-bit pattern. The syndrome value for these ten error patterns, asshown in the column of the polynomial e of FIG. 7 corresponding to thepolynomial e of FIG. 5, assumes ten different values of 22, 29, 20, 10,5, 24, 12, 6, 3 and 1. The polynomials a to h in FIG. 5 correspond tothe columns a to h of the generator polynomials a to h of FIG. 7,respectively. Thus, also in the other generator polynomials a to d and fto h, the syndrome values for ten error patterns indicate ten differentvalues, respectively. Therefore, the eight generator polynomials of FIG.5 are seen to be effective for error detection and correction.

The syndrome value 20 a and the syndrome value 20 b in FIG. 9 are inputto the error corrector 24 a and the error corrector 24 b, respectively.The corresponding error in the shift register output 22 is corrected bythe syndrome value 20 a in the error corrector 24 a and by the syndromevalue 20 b in the error corrector 24 b. The process for detecting anerror corresponding to the generator polynomial (X⁵+X⁴+X²+1) in e ofFIG. 5 and an error corresponding to the generator polynomial(X⁵+X⁴+X³+X²+1) in h of FIG. 5 is executed and, upon detection of theerror, a corresponding correction is carried out. The result is outputas an error detection/correction output 19 a and an errordetection/correction output 19 b, respectively.

An example of a more detailed configuration of the error correction unit24 a is shown in FIG. 13. The syndrome value 20 a is compared with tenvalues of 22, 29, 20, 10, 5, 24, 12, 6, 3, 1 by comparators 312 to 321.Upon coincidence by any comparator in the presence of an error, theresult is applied to a corresponding circuit of the exclusive ORcircuits 331 to 339 through a corresponding circuit of the OR circuits322 to 330. The exclusive OR circuits 331 to 339 are supplied with theinformation on the error position and the shift register output 22.Thus, the bit associated with the error is inverted, and the error iscorrected. The result is output as an error detection/correction output19 a.

Consider the error correcting operation in more detail. Assume, forexample, that the leading two bits of the sync pattern “010001011” areerroneous and the value “100001011” appears in the shift register output22. The error is that of the error pattern 2 in FIG. 7. The syndromevalue 20 a involved is 29 from FIG. 7. In FIG. 13, the result ofcomparison in the comparator 313 coincides and 1 (true value) is output.This value is input to the OR circuit 322 and the OR circuit 323, theoutput of which also assumes 1 (true value). As a result, one of theinput terminals of the exclusive OR circuits 331, 332 is suppliedwith 1. Thus, the two bits on the MSB side (corresponding to the head ofthe sync pattern) of the shift register output 22 are inverted, so that“100001011” is corrected to “010001011”. This pattern corrected isoutput as an error detection/correction output 19 a.

The error detection/correction outputs 19 a, 19 b are applied to thepattern matching units 27 a, 27 b of the data sync signal detector 3,and matched against the sync patterns of the sync pattern holders 26 a,26 b, respectively. Each sync pattern is given as a sync pattern 14, sothat the sync pattern holder 26 a holds a 9-bit pattern “010001011”, andthe sync pattern holder 26 b a 9-bit pattern “010001110”. For settingthe timing of the outputs of the pattern matching units 27 a, 27 b inorder, the output of the pattern matching unit 27 a is delayed throughthe unit time delay circuit 28 a and then applied to the majoritydecision logic circuit 29.

In the majority decision logic circuit 29, the number of coincidencesbetween two patterns is compared with the threshold value 15, and in thecase where the number of coincidences of the pattern matching is notless than the threshold value 15, the sync signal detection output 16 isproduced. In the case under consideration, the threshold value 15 is 2,and therefore a 2-input AND circuit can be used. When an error isdetected and corrected by the error detection/correction unit 6, thefact that the data starting position is unknown increases thepossibility of correcting the sync pattern erroneously. Thus thethreshold value is required to be 2 or more.

The sync signal detection output 16 gives the decode timing to thedecoder 4 of the MTR code. As a result, the correct decoding is realizedand the output data 17 is obtained.

Now, the performance of the embodiment shown in FIG. 9 will be describedagain with reference to FIG. 4. In the embodiment of FIG. 3, the errorpattern x could be saved. In the embodiment of FIG. 9, however, acontinuous 2-bit error can be detected and corrected, and therefore, theerror patterns xx, x00x can also be saved. In other words, it can beunderstood that by providing the (1+D) processing unit 5 and detectingand correcting the continuous 2-bit error after division into a bitstring of odd numbered bits and a bit string of even numbered bits,about 98.8% of the errors occurred can be saved and the detection rateof the data sync signal 92 can be improved further.

This performance will be explained with reference to FIGS. 17A, 17Bpartially used for reference above. Characteristic curves 174, 179represent the data sync signal detection error rate in the case wherethe data sync signal s detected under the conditions of the embodimentshown in FIG. 9. From FIG. 17A, it is seen that an improvement of about0.5 dB can be attained in terms of the signal-to-noise ratio of theViterbi decoder input as compared with the embodiment of FIG. 3. Also,let Be (abscissa) be the ratio of occurrence of an error event to thetotal number of output bits of the data discriminator 1 and Se(ordinate) be the ratio of occurrence of the data sync signal detectionerror to the number of requests for data sync signal detection. Thecharacteristic curve 179 for Be in the range of 0.1 or less isapproximated by equation (2) below.S _(e)=12B _(e) ^(1.42)  (2)

A signal processing apparatus according to still another embodiment ofthe invention will be explained with reference to FIG. 10. The basicconfiguration of FIG. 10 is the same as that of the embodiment shown inFIG. 9. Only the difference will be described in detail. The differencelies in a sync pattern 14, an error detection/correction unit 6 andgenerator polynomials used for them.

The sync pattern used in this case is an 18-bit pattern“000000100101010010” in the post code output 13. In the (1+D) processingoutput 18, on the other hand, an 18-bit pattern “000000110111111011” isinvolved. In the shift register output 22, the patterns are “000101111”and “000111101”. The generator polynomials for error detection andcorrection of these patterns are given as d(X⁵+X³+X²+X¹+1) andh(X⁵+X⁴+X³+X²+1) shown in FIG. 5.

The syndrome calculators 23 c, 23 d can be configured with an exclusiveOR circuit as in the embodiment shown in FIG. 9. The syndrome calculator23 c corresponds to the generator polynomial (X⁵+X³+X²+X¹+1), and thesyndrome calculator 23 d corresponds to the generator polynomial(X⁵+X⁴+X³+X²+1).

Now, the syndrome value 20 c for error patterns will be explained withreference to FIG. 8. FIG. 8 shows 19 error patterns of 1 bit or two.These are error patterns which appear in the shift register output 22,and include a 2-bit continuous error pattern which frequently appears asexplained in the embodiment of FIG. 9 and becomes a one-bit errorpattern occurring at the end of the 9-bit group. Next frequentlyappearing is the x0x error pattern which becomes one-bit error patternat the second bit from the end of the 9-bit group. For these 19 errorpatterns, there are 19 different syndrome values of 9, 26, 13, 17, 31,24, 12, 6, 3, 1, 19, 23, 28, 14, 7, 20, 10, 5 and 2 as shown in thecolumn of the generator polynomials d of FIG. 8 corresponding to thepolynomials d of FIG. 5. Also, for another generator polynomials h, thesyndrome values for 19 error patterns assume 19 different values insimilar fashion. It is seen therefore that two generator polynomials dand h in FIG. 5 are effective for two types of error detection andcorrection.

The syndrome values 20 c, 20 d of FIG. 10 are input to the errorcorrection units 25 c, 25 d, respectively. The corresponding error ofthe shift register output 22 is corrected by the syndrome value 20 c inthe error correction unit 25 c, and by the syndrome value 20 d in theerror correction unit 25 d. In respective cases, the error detection iscarried out in a way corresponding to the generator polynomial(X⁵+X³+X²+X¹+1) in d of FIG. 5, and corresponding to the polynomial(X⁵+X⁴+X³+X²+1) in h of FIG. 5. Upon detection of an error, thecorresponding correction is carried out. The result is output as anerror detection/correction outputs 19 c and 19 d.

An example configuration of the error correction unit 25 c is shown indetail in FIG. 14. The syndrome value 20 c is compared with 19 valuesincluding 19, 9, 23, 26, 28, 13, 14, 17, 7, 31, 20, 24, 10, 12, 5, 6, 2,3 and 1 by comparators 340 to 358. In the case where the output of anyone of the comparators is coincident in the presence of an error, theresult is applied to the corresponding one of the exclusive OR circuits384 to 392 through the OR circuits 359 to 383. The exclusive OR circuits384 to 392 are supplied with the error position information and theshift register output 22, and therefore, the bit associated with theerror is inverted thereby to correct the error. The result is output asan error detection/correction output 19 c.

Consider the error correction operation in more detail. Assume, forexample, that the 2nd and 4th bits from the head of the sync pattern“000101111” are erroneous so that the value “010001111” has appeared asthe shift register output 22. The error is that of the error pattern 13in FIG. 8. In this case, the syndrome value 20 c is 28 as seen from FIG.8. At the same time, in FIG. 14, the result of comparison in thecomparator 344 is coincident, and 1 (true value) is output. This valueis applied to the OR circuits 362, 367. Further, the signal is outputthrough the OR circuits 363, 369, so that the output also assumes 1(true value). As a result, 1 is input to one of the input terminals ofthe exclusive OR circuits 385, 387, and therefore the 2nd and 4th bitsfrom the MSB side (corresponding to the head of the sync pattern) of theshift register output 22 are inverted. Thus, the pattern “010001111” iscorrected to “000101111”. The pattern thus corrected is output as anerror detection/correction output 19 c.

The error detection/correction outputs 19 c, 19 d are input to thepattern matching units 27 c, 27 d of the data sync signal detector 3,and compared with the sync patterns of the sync pattern holders 26 c, 26d, respectively. Each sync pattern is given as a sync pattern 14, sothat the sync pattern holder 26 c holds the 9-bit pattern “000101111”and the sync pattern holder 26 d holds the 9-bit pattern “000111101”. Inorder to set the outputs of the pattern matching units 26 c, 26 d in thesame timing, the output of the pattern matching unit 27 c is delayedthrough the unit time delay line 28 c and input to the majority decisionlogic circuit 29.

In the majority decision logic circuit 29, the number of coincidences inthe result of the comparison between the two patterns obtained iscompared with the threshold value 15. In the case where the number ofcoincidences as a result of pattern matching is not less than the valuegiven by the threshold level 15, the sync signal detection output 16 isoutput. In this case, too, like in the embodiment of FIG. 9, 2 is givenas the threshold value 15, and therefore a two-input AND circuit can beused for this purpose.

The sync signal detection output 16 gives the decode timing of thedecoder 4 of the MTR code. As a result, the correct decoding isrealized, thereby producing the output data 17.

Once again, the performance of the embodiment shown in FIG. 10 isdescribed with reference to FIG. 4. In the embodiment of FIG. 9, theerror pattern x, the error pattern xx and the error pattern x00x can besaved. In the embodiment of FIG. 10, on the other hand, it is seen thatthe error pattern x0x can also be saved. Specifically, by inserting the(1+D) processing unit 5 and by detecting and correcting a 2-bitcontinuous error and a 3-bit continues error of x0x after division intoa bit string of odd numbered bits and a bit string of even numberedbits, it is understood that about 99.9% of the errors occurred can besaved, and the detection rate of the data sync signal 92 is furtherimproved.

This performance will be explained with reference to FIGS. 18A, 18B.FIGS. 18A, 18B are graphs mainly indicating the performance of theembodiment of FIG. 10, prepared by computer simulation.

In FIG. 18A, the abscissa represents the signal-to-noise ratio in theViterbi decoder input, and the ordinate the bit error rate and the datasync signal detection error rate. A characteristic curve 185 indicatesthe bit error rate of the data in the data discrimination output 12.This is a characteristic obtained when the data are regarded to berandom. A characteristic curve 181 indicates the characteristic of thedata sync signal detection error rate in the case where the data syncsignal is detected under the condition that all the 18 bits of the syncpattern are coincident. A characteristic curve 182 is based on a methodusing a reference technique not including the (1+D) processing unit fordata sync signal detection, and represents a characteristic of the datasync signal detection error rate in the case where the data sync signaldetection is carried out under the condition that any one of the 9-bitpatterns of the bit string of odd numbered bits and the bit string ofeven numbered bits are coincident. A characteristic curve 183 representsthe characteristic of the data sync signal detection error obtained inthe case where the data sync signal detection is carried out under thecondition ((1+D) processing unit 5 is included, and the errordetection/correction is not effected) of the embodiment of the inventionshown in FIG. 3. A characteristic curve 184 represents thecharacteristic of the data sync signal detection error obtained in thecase where the data sync signal detection is carried out under thecondition of the embodiment of the invention shown in FIG. 10. From FIG.18A, it is seen that the signal-to-noise ratio is improved by about 1 dBin the input of the Viterbi decoder as compared with the embodiment ofFIG. 3. This is seen to be an improvement of about 0.5 dB in thesignal-to-noise ratio as compared with the embodiment of FIG. 9.

In FIG. 18B, the abscissa represents the bit error rate in the datadiscrimination output 12, and the ordinate represents the data syncsignal detection error rate. This is the graph of FIG. 18A replottedwith the characteristic curve 185 used as the abscissa. A characteristiccurve 186 corresponds to the characteristic curve 181, a characteristiccurve 187 corresponds to the characteristic curve 182, a characteristiccurve 188 corresponds to the characteristic curve 183 and acharacteristic curve 189 corresponds to the characteristic curve 184.Let Be (abscissa) be the ratio of occurrence of an error event to thetotal number of output bits in the output of the data discriminator 1,and Se (ordinate) be the ratio of occurrence of a data sync signaldetection error to the number of requests for data sync signaldetection. The characteristic curve 189 for the value of Be in the rangeof 0.1 or less is approximated by equation (3) below.S _(e)=20B _(e) ^(1.64)  (3)

A signal processing apparatus according to a further embodiment of theinvention will be explained with reference to FIG. 11. The basicconfiguration of FIG. 11 is the same as that of the embodiment shown inFIG. 9. What is different is that four 9-bit patterns are used as a syncpattern 14. A method of detecting and correcting an error is also thesame as that of the embodiment shown in FIG. 9, and each sync patterncorresponds to ten error patterns for correction.

The sync patterns used in this embodiment include an 18-bit pattern of“100010010000010100” and an 18-bit pattern of “001000000010010100” inthe post-code output 13, and a total of 36-bit patterns are matched.Further, a 32-bit pattern of “10101010101010101010101010101010” forprevention of error propagation is inserted between the aforementionedtwo bit patterns. In the (1+D) processing output 18, these patterns arerepresented as “110011011000011110”, “001100000011011110” and“11111111111111111111111111111111”, respectively. The patterns matchedin the shift register output 22 include “101010011”, “101100110”,“010001011” and “010001110”. The generator polynomials for errordetection and correction of these patterns are given asf(X⁵+X⁴+X²+X¹+1), h(X⁵+X⁴+X³+X²+1), e(X⁵+X⁴+X²+1) and h (X⁵+X⁴+X³+X²+1),respectively.

The syndrome calculators 23 e to 23 h can be configured with exclusiveOR circuits as in the embodiment of FIG. 9. The syndrome calculator 23 ecorresponds to the generator polynomial (X⁵+X⁴+X²+X¹+1), the syndromecalculator 23 f corresponds to the polynomial (X⁵+X⁴+X³+X²+1), thesyndrome calculator 23 g corresponds to the polynomial (X⁵+X⁴+X²+1), andthe syndrome calculator 23 h corresponds to the polynomial(X⁵+X⁴+X³+X²+1). The syndrome calculators 23 f and 23 h are forcalculating the same generating polynomials, and therefore canalternatively be replaced by a single common syndrome calculator.

The syndrome value for ten error patterns for each pattern matched isthe value of the corresponding polynomial in the syndrome value columnin FIG. 7. Specifically, the syndrome value 20 e is given in the columnof the generator polynomial f, the syndrome value 20 f is given in thecolumn of the generator polynomial h, the syndrome value 20 g is givenin the column of the generator polynomial e, and the syndrome value 20 his given in the column of the generator polynomial h.

The syndrome values 20 e to 20 h in FIG. 11 are input to the errorcorrection units 24 e to 24 h, respectively. The corresponding error inthe shift register output 22 is corrected by the syndrome value 20 e inthe error correction unit 24 e, by the syndrome value 20 f in the errorcorrection unit 24 f, by the syndrome value 20 g in the error correctionunit 24 g, and by the syndrome value 20 h in the error correction unit24 h. In the respective cases, the error detection is carried out in amanner corresponding to the generator polynomial (X⁵+X⁴+X²+X¹+1) in f ofFIG. 5, the generator polynomial (X⁵+X⁴+X³+X²+1) in h of FIG. 5, thegenerator polynomial (X⁵+X⁴+X²+1) in e of FIG. 5, and the generatorpolynomial (X⁵+X⁴+X³+X²+1) in h of FIG. 5. Upon detection of an error,the corresponding correction is carried out. The result is output aserror detection/correction outputs 19 e to 19 h. A detailedconfiguration of the error correction units 24 e to 24 h is realized ina similar form to FIG. 13. In this case, too, the error correction units24 f and 24 h which perform a similar processing can alternatively bereplaced by a single common error correction unit.

The error detection/correction outputs 19 e to 19 h are input to thepattern matching units 27 e to 27 h, respectively, of the data syncsignal detector 3, and matched against the sync patterns of the syncpattern holders 26 e to 26 h, respectively. Each sync pattern is givenas the sync pattern 14, so that the sync pattern holder 26 e holds a9-bit pattern “101010011”, the sync pattern holder 26 f a 9-bit pattern“101100110”, the sync pattern holder 26 g a 9-bit pattern “010001011”,and the sync pattern holder 26 h a 9-bit pattern “010001110”. In orderto set the output timing of the pattern matching units 27 e to 27 h inorder, the output of the pattern matching 27 e is delayed by 51T (1T isa unit time) by the delay cell 28 e, the output of the pattern matching27 f by 50T by the delay cell 28 f, and the output of the patternmatching 27 g by 1T by the unit time delay cell 28 g. The result of eachdelay is input to the majority decision logic circuit 29.

The majority decision logic circuit 29 compares the number ofcoincidences of the four pattern matching results with the thresholdvalue 15, and in the case where the number of coincidences of thepattern matching result is not less than the figure of the thresholdvalue 15, a sync signal detection output 16 is output. In this case,too, the threshold value 15 is set to 2 as in the embodiment of FIG. 9.

The sync signal detection output 16 gives the decode timing for the MTRcode decoder 4. As a result, a correct decoding is realized and theoutput data 17 is obtained.

The performance for the embodiment of FIG. 11 will be explained. In theembodiment shown in FIG. 9, the detection cannot be carried out uponoccurrence of a single error pattern x0x or x000x. In the configurationunder consideration, however, the data signal detection of two or lesserrors of whatever type is possible for all the error patterns shown inFIG. 4. If only the error pattern x occurs, for example, the data syncsignal can be detected against five or less errors. Thus, it can beunderstood that the detection rate of the data sync signal 92 isremarkably improved.

The performance will be explained with reference to FIGS. 19A, 19B.FIGS. 19A, 19B are graphs showing the performance of the embodiment ofFIG. 11 as determined by computer simulation.

In FIG. 19A, the abscissa represents the signal-to-noise ratio of theViterbi decoder input and the ordinate the bit error rate and the datasync signal detection error rate. A characteristic curve 195 representsthe bit error rate of the data in the data discrimination output 12.This a characteristic obtained when the data are considered to berandom. A characteristic curve 191 represents the characteristic of thedata sync signal detection error rate when the data sync signaldetection is carried out under the condition that all the 36 bits of thesync pattern coincide. As compared with the characteristic curve 171 ofFIG. 17A or the characteristic curve 181 of FIG. 18A, it is seen thatthe detection performance is deteriorated somewhat by an amountequivalent to the increase in the number of bits of the matchingpattern. A characteristic curve 192 is based on a method of a referencetechnique not including the (1+D) processing unit 5 for data sync signaldetection, and represents the characteristic of the data sync signaldetection error rate in the case where the data sync signal detection iscarried out under the condition that any one of the four 9-bit patternsseparated into a bit string of odd numbered bits and a bit string ofeven numbered bits is coincident. A characteristic curve 193, on theother hand, represents a characteristic of the data sync signaldetection error rate in the case where the data sync signal detection iscarried out under the condition (the (1+D) processor 5 is included, andno error is detected or corrected) of the embodiment of FIG. 3. Acharacteristic curve 194 represents the characteristic of the data syncsignal detection error rate in the case where the data sync signal isdetected under the condition of the embodiment of FIG. 11 according tothe invention. From FIG. 19A, it is seen that the signal-to-noise ratiois improved by about two or three dB as compared with the configurationof the reference technique.

In FIG. 19B, the abscissa represents the bit error rate in the datadiscrimination output 12, and the ordinate represents the data syncsignal detection error rate. This is the result of replotting the graphof FIG. 19A with the characteristic curve 195 as an abscissa. Acharacteristic curve 196 corresponds to the characteristic curve 191, acharacteristic curve 197 corresponds to the characteristic curve 192, acharacteristic curve 198 corresponds to the characteristic curve 193,and a characteristic curve 199 corresponds to the characteristic curve194. Let Be (abscissa) be the ratio of occurrence of an error event tothe total number of output bits in the output of the data discriminator1, and let Se (ordinate) be the rate of occurrence of the data syncsignal detection error to the number of requests for data sync signaldetection. The characteristic curve 198 for Be in the range of 0.1 orless is approximated by equation (4), and the characteristic curve 199for Be in the range of 0.1 or less is approximated by equation (5).S _(e)=90B _(e) ^(2.51)  (4)S _(e)=160B _(e) ^(3.15)  (5)

As explained in the embodiments of FIGS. 3, 9, 10, 11, the pattern usedas a sync pattern is required to have the remainder of zero in thedividing operation by the generator polynomial shown in FIG. 4, andthese operations are required to make no error of easily employing otherpatterns. Such 9-bit patterns are listed in FIG. 16. In this case, 44types of patterns are available. The patterns used in the embodiments ofFIGS. 3 and 9 are Nos. 15 and 17 in FIG. 16, the patterns used in theembodiment of FIG. 10 are Nos. 3 and 7 in FIG. 16, and the patterns usedin the embodiments of FIG. 11 are Nos. 15, 17, 33 and 37 in FIG. 16.

When an attempt is made to realize the data sync detector in the signalprocessing apparatus according to the invention with an integratedcircuit, the circuit size, when a 2-input NAND gate is converted as onegate, increases about 10 gates for the embodiment of FIG. 3, about 200gates for the embodiment shown in FIG. 9, about 350 gates for theembodiment shown in FIG. 10, and about 400 gates for the embodimentshown in FIG. 11, as compared with the reference technique. This iseasily realizable taking the recent progress of the integrated circuittechnology into account.

The data sync signal detector according to the invention can also beconfigured and realized in software as described later.

As described above, with the signal processing apparatus according tothe invention, the (1+D) processing is executed before detection of thedata sync signal, and further the bits are divided into a bit string ofodd numbered bits and a bit string of even numbered bits. In this way,the types of error patterns can be reduced and the error pattern lengthshortened. As a result, the error detection and correction isfacilitated, thereby making possible more accurate data sync signaldetection.

As shown in FIGS. 17A, 17B, 18A, 18B, 19A, 19B, the method of detectingthe data sync signal for the signal processing apparatus according tothe invention, as compared with the method of the reference technique,has an effect of improving the signal-to-noise ratio in the input of theMaximum-Likelihood or Viterbi decoder by about 2 to 3 dB. Thus, it ispossible to obtain data sync information with high accuracy. Also, thedata error caused by the error of the data sync information of thesignal processing circuit, the information recording/reproductionapparatus or the information transmission system using the data syncinformation can be reduced.

Now, a further embodiment of the invention will be explained withreference to FIG. 22.

In FIG. 22, input data 11 are input to a data discriminator 1, and adata discrimination output 12 providing a code bit output discriminatedby the data discriminator 1 is input to a post-coder 2 and subjected toa predetermined post-code processing. Further, the output 13 of thepost-coder 2 is input to a decoder 4 and an error detection/correctionunit 6. The error detection/correction unit 6 detects and corrects anerror of bit strings grouped in one or more groups of bit stringaccording to a predetermined method. The output 19 thus corrected inerror is input to a data sync signal detector 3, matched against a syncpattern 14. In the case where the number of pattern coincidences is notless than the threshold value 15, a sync signal detection output 16 isoutput. The sync signal detection output 16 is input to the decoder 4,and gives a decode timing of the code string in the post-code output 13.Thus, the demodulated output data 17 is produced from the decoder 4.

An error of the data sync signal is detected and corrected before datasync signal detection and therefore the data sync signal can beaccurately detected.

A yet further embodiment of the invention will be explained withreference to FIG. 23.

The configuration of FIG. 23 is similar to that of the embodiment shownin FIG. 9. However, the difference lies in that the (1+D) processingunit 5 is not included, the data discriminator 1 is a Viterbi decoder ofordinary EEPRML type not optimized for the MTR code, the post coder 2has the characteristic of (1+D)², and the code applied to the decoder 4is of GCR (Group Code Recording) (for example, “RATE 16/17 (0, 6/6)” IBMTechnical Disclosure Bulletin Vol. 31, No. 8, January 1989, pp. 21-23).Also, the sync pattern used is the same 18-bit pattern as in theembodiment of FIG. 9, and two sync patterns “0011111111100011000” and“110000000011100111” are available in the data discrimination output 12.Due to the difference in the characteristic of the post coder 2,however, the sync pattern in the post code output 13 is a 18-bit patternof “001100000011011110”.

The post code output 13 is input to a shift register 21 in the errordetection/correction unit 6. The configuration of the errordetection/correction unit is the same as that in the embodiment of FIG.9. Thus, the shift register 21, the syndrome calculator 2 a, thesyndrome calculator 23 b, the error correction unit 24 a and the errorcorrection unit 24 b included in the error detector/corrector 6 are alsothe same as the corresponding parts of the embodiment of FIG. 9.

The sync signal detection output 16 provides the decode timing for thedecoder 4 of the GCR code. As a result, a correct decoding is realizedand the output data 17 is produced.

Even in the case where the MTR code or the GCR code is used as the datamodulation code, a data sync pattern which improves the performance ofthe data sync signal detection can be selected. The same pattern can beused in this case. In addition, due to the presence of the particularpattern in each code, this embodiment can be configured the same way asthe embodiment of FIG. 9. The performance of the data sync signaldetection is also substantially the same. The performance of the datasection, however, is varied depending on the code used.

In this embodiment, the output of the post coder is grouped into a bitstring of even numbered bits and a bit string of odd numbered bits andmatched. The data sync signal detector can be configured with the errordetection and correction function, however, in which the output of thepost-coder is divided into one or more groups of bit string by a methodother than dividing it into a bit string of odd numbered bits and a bitstring of even numbered bits. Nevertheless, such a configurationinvolves more error patterns and is complicated as compared with theembodiment under consideration, with the performance thereof inferior tothis embodiment as correctable error patterns are limited.

A still further embodiment of the invention will be explained withreference to FIG. 24.

The basic configuration of FIG. 24 is the same as that of the embodimentshown in FIG. 13. The difference, however, lies in the configuration ofthe shift register 21, the manner in which the shift register output 22is produced, the manner in which the shift register output 22 is inputto the syndrome calculator 23, the manner in which the shift registeroutput 22 is applied to the error correction unit 24, and the absence ofthe delay circuit. The illustrated arrangement is also different.

The shift register 21 has a length of 68 bits.

Nine bits including every other bit from the MSB side (farthest from theinput of the (1+D) processing output 18) of the shift register 21constitute a shift register output 22 e and applied to the syndromecalculator 23 e and the error correction unit 24 e. The 9 bits one bitnearer to the LSB side (the side where the (1+D) processing output 18 isinput) of the shift register output 22 e constitutes the shift registeroutput 22 f and are applied to the syndrome calculator 23 f and theerror correction unit 24 f. Nine bits including every other bit from theLSB side of the shift register 21 constitute the shift register output22 h and are applied to the syndrome calculator 23 h and the errorcorrection unit 24 h. The 9 bits one bit nearer to the MSB side of theshift register output 22 h constitutes the shift register output 22 g,and are applied to the syndrome calculator 23 g and the error correctionunit 24 g.

The shift register 21 is lengthened and the output retrieve positionthereof is selected, so that the shift register 21 can have the functionand effect of the delay circuits 28 e to 28 g in the embodiment of FIG.13. This effect can eliminate the delay lines 28 e to 28 g. The shiftregister may be less than 68 bit length, for example, 36 or 37 or morebit length so that the register output is divided in groups with 0 or 1or more bits of an arbitrary pattern interposed therebetween.

The configuration of FIG. 24 is exactly equivalent to the configurationof the embodiment shown in FIG. 11.

With reference to FIG. 25, a yet further embodiment of the inventionwill be explained.

FIG. 25 is a flowchart for realizing, by software, a data sync signaldetector having the configuration of the embodiment shown in FIG. 9. Thefunctions to be realized are the same as those of the embodiment of FIG.9, and so are the data sync pattern and the method of error detectionand correction.

First, the process starts from step 401, and the initialization requiredfor data sync detection is performed in step 402. The storage startingaddress adr of the memory for storing the value of the post-code outputdata is set to the value of AD, the program control count cnt to zeroand the program control count limit value to L.

Then, in step 403, the post-code output data 13 is stored from addressAD of the memory. The memory can sufficiently store the portions beforeand after the data involved.

In step 404, the data of 18 bits or more are read out of the address ADof the memory and the calculation (1+D) is performed.

In step 405, 9 bits are retrieved from every other position from theaddress (AD+cnt).

In step 406, the syndrome value is calculated from the particular 9bits. This calculation is equivalent to 23 a of FIG. 9. It is determinedin step 407 whether the syndrome value thus calculated is zero or not.In the case where the syndrome value is zero, the process proceeds tostep 410. In the case where the syndrome value is not zero, on the otherhand, it is determined in step 408 whether the error can be correctedfrom the particular syndrome value. If the error cannot be corrected, onthe other hand, the process proceeds to step 419. The error, ifcorrectable, is corrected in step 409.

Then, the pattern is compared with the pattern A in step 410. It isdetermined in step 411 whether the result of comparison is coincident ornot, and if not coincident, the process proceeds to step 419, otherwiseto step 412.

In step 412, 9 bits including every other bit from are retrieved fromthe address (AD+cnt+1) of the data read from the memory and subjected tothe (1+D) calculation in step 404.

In step 413, the syndrome value is calculated from the particular 9bits. This calculation is equivalent to 23 b of FIG. 9. It is determinedin step 414 whether the calculated syndrome value is zero or not. If thesyndrome value is zero, the process proceeds to step 417. Otherwise, itis determined in step 415 whether the error is correctable from theparticular syndrome value. If the error is not correctable, the processproceeds to step 419, otherwise, the error is corrected in step 416.

Then, the pattern is compared with the pattern B in step 417. It isdetermined in step 418 whether the result of comparison is coincident ornot, and if not coincident, the process proceeds to step 419. Otherwise,the process proceeds to step 421.

In step 421, both the matching patterns A and B are coincident,indicating that the data sync signal detection is possible.

Then in step 422, the head address of the data is determined from theprogram control count cnt and the process is terminated in step 424.

In the case where the data sync signal is not detected, the processproceeds to step 419, where 1 is added to the program control count cnt,and it is determined in step 420 whether this program control count cntis not more than the program control count limit. If it is within thelimit, the process returns to step 404 for proceeding with the data syncsignal detection. By adding 1 to the program control count cnt, thesyndrome value can be calculated or the bit position for patternmatching can be displaced bit by bit.

In the case where the determination in step 420 is that the programcontrol count cnt exceeds the limit, on the other hand, the data syncsignal detection is impossible, and the fact is reported in step 423,with the process terminated in step 424. The program control count limit“limit” represents and defines the range where the data sync signal canbe stored in memory.

The foregoing description refers to the case where the data sync signaldetector according to the embodiment of FIG. 9 is realized in software.Nevertheless, the other embodiments can of course be realized also insoftware. It is also possible to realize the software as acomputer-readable program embodied on the recording medium.

FIG. 15 is a block diagram showing an example configuration of amagnetic disk device according to an embodiment of the invention. Themagnetic disk device shown in FIG. 15 uses a signal processing apparatusaccording to the invention described above.

The magnetic disk device 201 comprises a magnetic disk 211 providing adata recording medium, a magnetic head 212 for recording/reproducingdata on the magnetic disk 211, a R/W amplifier 213 for amplifying thedata signal recorded/reproduced, a HDC (Hard Disk Controller)microcomputer 214 for performing the I/F control with a host system 202and the control operation, etc. for the whole system, a data buffer 215for temporarily storing the data exchanged with the host system 202, aservo processing circuit 216 for processing the servo control signalrecorded in the magnetic disk 211, a mechanism driver 217 forcontrolling a motor 219 for rotationally driving a magnetic disc 211 ora VCM (Voice Coil Motor) 218 which sets the magnetic head 212 inposition based on a command from the servo processing circuit 216, and asignal processing circuit 220 for coding and modulating the datarecorded in the magnetic disk 211 and decoding the data read from themagnetic disk 211.

The signal processing circuit 220 is configured with the signalprocessing apparatus according to the embodiments of FIGS. 3, 9, 10, 11,23, 24 or 25 or a modification thereof, and includes a data sync signaldetector 221. The magnetic disk device 201 having this configuration canbe realized with a small detection error rate of the data sync signal.

Specifically, the recording density of the magnetic disk 211 can beimproved by employing the signal processing system such as a datadiscriminator including a Viterbi decoder, and at the same time, theerror rate can be reduced by improving the data sync signal detectionperformance by the employment of the data sync signal detector 221 atthe same time.

Also, the production cost is reduced by reducing the circuit size of thesignal processing system for detecting the data sync signal such as thedata sync signal detector 221 while at the same time reducing the errorrate by improving the data sync signal detection performance.

The invention developed by the present inventor has been describedspecifically above based on embodiments thereof. The present invention,however, is not limited to the embodiments described above but can bemodified in various ways without departing from the scope and spirit ofthe invention.

In the foregoing description, for example, the data sync signaldetection system of the signal processing apparatus according to theinvention is referred to as an example of a magnetic disk device. Inaddition to the magnetic disk device, however, the invention can be usedwith an information processing signal processing circuit, an integratedcircuit, a magneto-optic device, a floppy disk drive, etc. with equaleffect.

The features of the invention other than those described in the appendedclaims are as follows.

A 2-bit continuous error and a one-bit error at the ends of the groupcan be detected and corrected by the error detection/correction unit.

The 2-bit error having an error pattern x0x (x indicates an error bit,and 0 a bit not an error) and the one-bit error at the second positionfrom each end of the group can be detected and corrected by the errordetection/correction unit (FIG. 8).

The data sync signal is detected in the case where the threshold valuefor data sync signal detection is set to 2 and the number of coincidentbit string groups is 2 or more (FIGS. 9 to 11).

The signal processing apparatus is formed of integrated circuits.

The signal processing system of signal processing apparatus according tothis invention is used with the magnetic disk device, themagneto-optical disk device or the optical disk device.

In a signal processing apparatus according to the embodiments describedabove, the detection error can be reduced in the data sync signaldetection.

Also, the signal processing apparatus described in the embodiments abovehas the effect of improving the data sync signal detection performanceof the data sync signal detector with the improvement of thereproduction performance of the data section.

Further, the configuration of the data sync signal detector is simpleand the circuit size can be reduced.

In the magnetic disk drive according to the aforementioned embodiments,the recording density is improved by the employment of a signalprocessing system including a Maximum-Likelihood or Viterbi decoderwhile at the same time reducing the error rate by the improvement of thedata sync signal detection performance.

Also, in the magnetic disk device according to the above-mentionedembodiments, the production cost is reduced by the reduced circuit sizeof the signal processing system for detecting the data sync signal andthe error rate can be reduced by the improved data sync signal detectionperformance at the same time.

1. A data processing device comprising: a discriminator fordiscriminating input data and outputting discriminated data; a decoderfor decoding data based on the discriminated data and outputting decodeddata; a (1+D) processor for processing data based on the discriminateddata and outputting (1+D) processed data; a detecting/correctingprocessor for detecting/correcting error of the (1+D) processed data andoutputting detected/corrected processed data; and a data sync signaldetector for detecting a data sync signal of the detected/correctedprocessed data in comparison with predetermined sync pattern andoutputting a detected data sync signal to the decoder, wherein thedecoder decodes the data when receiving the detected data sync signal.2. The data processing device according to claim 1, wherein thepredetermined sync pattern includes two 9-bit patterns.
 3. The dataprocessing device according to claim 2, wherein each of the 9-bitpatterns is configured with a 4-bit code and a 5-bit Cyclic RedundancyCheck Code corresponding to the 4-bit code.
 4. The data processingdevice according to claim 2, wherein a remainder of each of the 9-bitpatterns divided by a generator polynomial of degree 5 is zero.